基于双线性插值的FPGA缩放算法源码

`timescale 1ns/1ps
modulescaler#(
parameterSRC_HIGH=512,
parameterSRC_WIDTH=640,
parameterDST_HIGH=768,
parameterDST_WIDTH=960,
parameterWIDTH=8,
parameterCOE=16
)(
inputclkin,
inputrst_n,
inputvs_in,
inputde_in,
input[WIDTH-1:0]din,
outputreg[WIDTH-1:0]dout,
outputregde_out,
outputregvs_out
);

localparamH_COE=2**COE*SRC_WIDTH/DST_WIDTH;
localparamV_COE=2**COE*SRC_HIGH/DST_HIGH;

regrst_in_r1 , rst_in_r2;

always @ (posedge clkin or negedge rst_n)begin
if(rst_n == 1\’b0)begin
rst_in_r1<=1\’b0;
rst_in_r2<=1\’b0;
end else begin
rst_in_r1<=rst_n;
rst_in_r2<=rst_in_r1;
end
end

reg[11:0]wr_addr;
reg[11:0]wr_addr_tq;
regwr_en1;
regwr_en2;
regwr_en3;
regwr_en4;
reg[11:0]cnt_v;
reg[WIDTH-1:0]din_r1;
reg de_r1;

always @ (posedge clkin)begin
if(rst_in_r2 == 1\’b0)begin
wr_addr_tq<=12\’d0;
end else if(de_in & wr_addr_tq >= SRC_WIDTH-1)begin
wr_addr_tq<=12\’d0;
end else if(de_in)begin
wr_addr_tq<=wr_addr_tq + 1\’d1;
end
wr_addr <= wr_addr_tq;
din_r1<=din;
de_r1 <= de_in;
end

always @ (posedge clkin)begin
if(rst_in_r2 == 1\’b0)begin
cnt_v<={$clog2(SRC_HIGH){1\’b0}};
end else if(de_in & cnt_v >= SRC_HIGH-1 & wr_addr_tq >= SRC_WIDTH-1)begin
cnt_v<={$clog2(SRC_WIDTH){1\’b0}};
end else if(de_in & wr_addr_tq >= SRC_WIDTH-1)begin
cnt_v<=cnt_v + 1\’d1;
end
end

always @ (posedge clkin)begin
if(rst_in_r2 == 1\’b0)begin
wr_en1<=1\’b0;
end else if(cnt_v[1:0] == 2\’b00)begin
wr_en1<=de_in;
end else begin
wr_en1<=1\’b0;
end
end

always @ (posedge clkin)begin
if(rst_in_r2 == 1\’b0)begin
wr_en2<=1\’b0;
end else if(cnt_v[1:0] == 2\’b01)begin
wr_en2<=de_in;
end else begin
wr_en2<=1\’b0;
end
end

always @ (posedge clkin)begin
if(rst_in_r2 == 1\’b0)begin
wr_en3<=1\’b0;
end else if(cnt_v[1:0] == 2\’b10)begin
wr_en3<=de_in;
end else begin
wr_en3<=1\’b0;
end
end

always @ (posedge clkin)begin
if(rst_in_r2 == 1\’b0)begin
wr_en4<=1\’b0;
end else if(cnt_v[1:0] == 2\’b11)begin
wr_en4<=de_in;
end else begin
wr_en4<=1\’b0;
end
end

regstart;
reg[3:0]state , next_state;
localparamIDLE=4\’b0000;
localparamWAIT=4\’b0001;
localparamWORK=4\’b0010;
localparamJUDGE=4\’b0011;
localparamDONE=4\’b0111;

always @ (posedge clkin)begin
if(rst_in_r2 == 1\’b0)begin
start<=1\’b0;
end else if(wr_en2 & wr_addr >= SRC_WIDTH